1. Field of the Invention
The embodiments of the invention generally relate to methods for forming integrated circuit structures and, more specifically, to a methodology that utilizes sidewalls of doped silicon mandrels to pattern underlying layers.
2. Description of the Related Art
Fabrication of integrated circuits usually requires forming multiple patterns, including sublithography patterns, on the same chip. For example, fin-type field effect transistors (FinFETs) have been emerging as a promising new approach for continued scaling of complementary metal oxide semiconductor (CMOS) technology. Sidewall spacer imaging transfer (SIT) is one of the common methods for forming narrow fins beyond the printing capability of optical lithography. Conventional SIT methods form all fins to have the same width across the chip. Some applications, however, require fins with different widths on the same chip. For example, various FinFET devices on the same chip may require different fin width for different threshold voltages. In another example, FinFET devices may be formed on the same chip with other devices such as tri-gate devices or planar devices which require different fin widths than the fin width for FinFET devices.